Abstract

The transition to a globalized, fabless semiconductor manufacturing model has integrated third-party foundries and external intellectual property (IP) vendors into the integrated circuit (IC) design cycle. While this collaborative system promotes innovation, it also exposes layouts to security threats. Protecting these designs is paramount; however, applying traditional encryption methodologies fundamentally alters the syntactic hierarchy of the industry-standard GDSII stream format, causing electronic design automation (EDA) tools to crash. Furthermore, a full encryption hinders modern system-on-chip (SoC) development, where different teams require access to specific modules of the design, without exposing the entire IP. To resolve this issue between collaborative layout sharing and zero-trust security, this paper presents a software implementing an encryption engine. By applying the NIST-standardized FF1 Format-Preserving Encryption (FPE) algorithm directly to the geometric data, the proposed software obfuscates sensitive spatial coordinates and structural nomenclature while maintaining the native GDSII format. The engine embeds multi-tiered cryptographic access control directly into the layout, utilizing native metadata properties. This framework allows proprietary logic to be securely compartmentalized, ensuring that interacting parties only view the specific structures they possess the clearance to decrypt.

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