Abstract

This work presents a power-friendly framework for efficient manufacturing test of dynamic voltage and frequency scaling (DVFS)-based 3D Systems-on-Chip (SoCs). The proposed approach employs a through-silicon via (TSV)-based inter-layer test architecture to enable compact and high-speed delivery of test data across stacked dies, while a bus-based space- and time-division multiplexing (SDM/TDM) mechanism distributes test data within each layer. Based on this architecture, a test access mechanism (TAM) optimization method is introduced to reduce TSV usage, improve bandwidth utilization, and minimize test application time. The optimization process uses effective pruning criteria to limit the exploration of inefficient TAM configurations while preserving promising design alternatives. In addition, advanced test-scheduling methods are developed to exploit TDM-based parallelism and flexibility, while explicitly enforcing power constraints at the SoC, layer, and voltage-island levels. These scheduling methods combine fast heuristic construction with metaheuristic optimization techniques to improve solution quality without excessive computational cost. Experimental evaluation on artificial DVFS-based 3D SoC instances demonstrates that the proposed framework achieves reductions in TSV count and effectively limits the overall test time compared with baseline approaches. The results confirm that jointly considering TAM design, DVFS-aware scheduling, and power constraints provides an effective and scalable solution for testing complex DVFS-based 3D SoCs.

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